Embodiments of the invention relate generally to integrated circuit packages and, more particularly, to embedded chip build-up that uses low resistance metal interconnects directly to the chip bond pad or electrical component connection pad, allowing higher device speeds, lower power consumption, and smaller size. Embedded chip packages can be manufactured having a plurality of chips or electronic components in a stacked 3D arrangement. The plurality of chips or electronic components are electrically connected to an input/output system by way of metal interconnects routed through a plurality of laminate re-distribution layers.
As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flipchip packages, and now embedded chip build-up packaging. Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
With chip scale packages incorporating multiple, stacked chips, the chips are typically wire-bonded to the substrate, resulting in high electrical resistance, inductance and capacitance, causing degraded device speed and higher power consumption. Flipchip die can not be easily 3D stacked and are mostly limited to side-by-side planar die arrangements, which use large package area or package stacking, thereby causing tall 3D structures. Chips that are sequentially stacked and wirebonded can not be pre-tested as a separate packaged chip, allowing for compounded device final test loss and assembly yield loss that increases production cost.
Advancements in IC chip packaging requirements also pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an increased number of re-distribution layers, with eight or more re-distribution layers being common. The standard embedded chip build-up process, in which the one or more dies are initially placed on the IC substrate and the re-distribution layers are subsequently applied in a layer-by-layer fashion, can lead to warpage in the rerouting and interconnection system, requiring the use of a molded epoxy stress balance layer or metal stiffener.
Accordingly there is a need for a method for embedded chip fabrication that allows for the application of multiple dies in a stacked arrangement with improved electrical interconnect performance. There is a further need for embedded chip fabrication that provides a shorter manufacturing cycle time and allows for the application of multiple re-distribution layers while minimizing warpage of the package without the use of a stiffener.